Maybe CLK problems ???
Date: Thursday, May 30 2013 @ 07:13:57 UTC
Topic: Amiga FPGA accelerator


After huge investigation I found out that my design can't run on higher frequencies. Maximum frequency possible is 87.5MHz. System can't work on any higher frequency even on 90MHz is unstable. Best results I come to regarding performance was 6.88Mips at that 87.5MHz and it is achieved when code optimization is done. That's about it! So then I started to wonder that maybe something is wrong with only signal I really need to be stable and coming from Amiga motherboard, 7MHz clock signal. Every other signal is not so important regarding timings and can be adjusted if needed inside FPGA but getting basic clock from Amiga motherboard is essential because we need to have proper detection of rising and falling edges of that clock so we can, using them, define read and write states in MC68K bus cycles. So what I needed is to have Amiga motherboard clock more stable because in process of attaching that clock to FPGA I needed to use ALVC device to solve CMOS to LVCMOS translation. But ALVC device gives delay to Amiga clock and it could make signal unstable. So I needed new approach to introduce 7MHz clock to FPGA and in the same time I needed to solve CMOS to LVCMOS translation without ALVC device to save FPGA from damaging I/O pin. I decided to use BAT54S diode who will protect FPGA I/O from higher voltages and in the same time we will have 7MHz clock inside FPGA without major delay and this time delay will be dependent only from length of copper trace between Amiga motherboard and FPGA. Now, because clock is stable it can be easily adjusted inside of FPGA so rising and falling edges of that clock can be properly detected. Compared 7MHz signals, one coming thru ALVC device and one protected with BAT54S, you can see on picture attached. So maybe this is potential problem ?







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