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Vampire 600 V1: Bus is mine!
Posted on Saturday, December 08 2012 @ 17:41:27 CST by majsta

Since I separated my project into few small ones only success! It took me only half an hour to implement this part. The goal was simple, disable on board MC68K CPU and replace it with some kind of mini CPU who will only write something on color register. Sounds simple? It took me about 532 lines of code to create something like this.


Those are the stages:
1. First Finite State Machine started.
2. Complete system started with ALVC devices disabled.
3. Amiga system restarted using counters.
4. Finite State Machine who is dedicated for 3-wire bus arbitration enabled.
a) FSM check reset signal and count bus cycle.s
b) FSM asserts BR
c) FSM waits to current cycle is complete (AS and DTACK negated, BG asserted) and asserts BGACK
d) FSM release BR.
e) FSM activate reset signal who enables mini CPU who will write to color register.
4. First FSM check that reset is enabled.
5. ALVC devices are programmed to support Address Bus, AS, LDS, UDS and RW signals as output FPGA signals. In the same stage AS, LDS, UDS and RW pulled high.
6. Write dff180 to Address Bus (Amiga color register).
7.Pull AS low to indicate that valid address is placed and RW low indicating write cycle.
8.Set ALVC devices dedicated for Data Bus as output, check counter and regarding on state of counter write on Data Bus 0f00 for red and 000f for blue color enabling and disabling LED.
9. Pull UDS and LDS low to indicate that valid data is on the bus but if DTACK is low release AS, UDS, LDS and leave RW for another cycle.
10. Pull RW high and set ALVC devices dedicated for Data Bus for input FPGA signals. Restart counter and back to stage 6.


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